Method of manufacturing a non-volatile memory device
US8114735B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2007 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Jul 8, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02337
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be performed using a first gas including nitrogen and a second gas including oxygen to remove defect sites in the charge trapping layer and to densify the charge trapping layer. A blocking layer may be formed on the heat-treated charge trapping layer, and a conductive layer may then formed on the blocking layer. The blocking layer, the conductive layer, the heat-treated charge trapping layer and the tunnel insulating layer may be patterned to form a gate structure on the channel region. Accordingly, data retention performance and/or reliability of a non-volatile memory device including the gate structure may be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.