Semiconductor wafer scale package system
US8114771B2 · kind B2 · utility
2Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2006 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | May 25, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer scale package system is provided including providing a semiconductor substrate having a through-hole via with a conductive coating, forming a filled via by filling the through-hole via with a conductive material, coupling a package substrate to the filled via, and singulating a chip scale package from the semiconductor substrate and the package substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.