Fuse structure and method for manufacturing same
US8115274B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2007 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Jan 27, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface, and a planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and including multiple barrier layers of different materials, wherein the fuse conductive trace, the metallization layer and the barrier multilayer assembly are arranged such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.