Lead frame for semiconductor device
US8115288B2 · kind B2 · utility
3Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2011 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Feb 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A lead frame for reducing detrimental effects of burr formation includes a lead frame that has leads where a portion of a top surface is removed from a first lead and a portion of a bottom surface is removed from a second lead adjacent to the first lead to reduce spacing between leads while reducing the detrimental effects of burr formation, such as shorting and the like, caused during singulation of a semiconductor device manufactured with the lead frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.