Flip chip package maintaining alignment during soldering
US8115319B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2010 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Aug 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a flip chip package maintaining alignment during soldering, primarily comprising a chip and a substrate. A plurality of bumps and at least an extruded alignment key are disposed on the active surface of the chip. The substrate has a plurality of bonding pads and at least an alignment base where the alignment base has a concaved alignment pattern corresponding to the extruded alignment key. When the chip is disposed on the substrate, the extruded alignment key is embedded into the concaved alignment pattern to achieve accurately align the bumps to the corresponding bonding pads. Therefore, even with the mechanical misalignment due to the accuracy of flip-chip die bonders and the transportation during reflow processes, the bumps of a chip still can accurately align to the bonding pads of the substrate to achieve accurate soldering which is especially beneficial to the mass production of MPS-C2 products.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.