Semiconductor package and method of manufacturing the semiconductor package
US8115323B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2008 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Oct 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package and a method of manufacturing the package are provided. The semiconductor package comprises: a mounting substrate including a bond finger; at least one semiconductor chip disposed on the mounting substrate, the semiconductor chip including a bonding pad; a first molding member disposed on the mounting substrate so as to cover the bond finger and the bonding pad, the first molding member including an interconnection path disposed inside the first molding member so as to connect the bond finger to the bonding pad; a conductive element disposed in the interconnection path; and a second molding member overlying the first molding member. The interconnection path can be formed by a laser process. The conductive element can be formed by conductive nanoparticles or metal wires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.