Patent · US Active

Circuit arrangement for filtering unwanted signals from a clock signal, processing system and method of filtering unwanted signals from a clock signal

US8115516B2 · kind B2 · utility

2Cited by

4References

19Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Hubert M. Bode · Haar, DE
Andreas Laudenbach · Alzenau, DE
Andreas Roth · Gunzenhausen, DE
Engelbert Wittich · Wartenberg, DE

Key dates

Filing date	Jun 14, 2007
Grant date	Feb 14, 2012
Priority date	—
Expiry date	Feb 2, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH03K5/1252
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A circuit arrangement for detecting unwanted signals on a clock signal comprises an input for receiving the clock signal, and a Phase Lock Loop PLL circuit having a reference input coupled to the input of the circuit arrangement for receiving the clock signal and an output for providing a PLL output signal. The circuit arrangement further comprises a detector coupled to the output of the PLL circuit and to the input of the circuit arrangement. The detector is arranged to identify correct transitions in the clock signal using the PLL output signal, and to remove incorrect transitions due to unwanted signals from the clock signal so as to provide a filtered clock signal at an output of the circuit arrangement.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.