Multi-level storage algorithm to emphasize disturb conditions
US8116151B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 11, 2008 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Dec 15, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5628
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Providing systems and methods that reduce memory device read errors and improve memory device reliability by intelligently disturbing the memory cells during storage of their characteristic states. A specification component can determine a desired characteristic state for each cell of a plurality of multi-cell memory devices. A storage component can, alternatively, successively store an equivalent characteristic state in each cell of the plurality of multi-cell memory devices in stages, based on a cell's current characteristic state, or directly store the desired characteristic state of each cell of the plurality of multi-cell memory devices, based on an ordering of desired characteristic states of cells of the multi-cell memory devices. Further, a step component can gradate the equivalent characteristic state between successive storage stages. In this way, the overlap of distributions of electrical characteristics associated with different bits of one or more memory cells can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.