System and method for refreshing a DRAM device
US8116161B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2007 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Oct 13, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40611
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a system and method for refreshing a DRAM device without interrupting or inhibiting read and write operations of the DRAM device. The system may includes refresh control circuitry that selectively generates requests to perform refresh operations and a refresh address counter that is coupled to the refresh control circuitry and that generates a refresh address in response to receiving a refresh request. The refresh address corresponds to a word line of the DRAM array to be refreshed. Address control and switching circuitry may be coupled to the refresh control circuitry. The address control and switching circuitry selectively transmits read/write addresses and refresh addresses to the DRAM array, in order to perform refresh operations on the DRAM array without inhibiting read and write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.