Dynamic signal calibration for a high speed memory controller
US8116162B1 · kind B1 · utility
8Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2010 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Aug 29, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1774
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Within an integrated circuit comprising a memory controller, a method can include, responsive to determining that the memory controller is performing a refresh operation, calculating a new tap setting according to a new maximum value and an old tap setting of the delay circuit. The new maximum value specifies a number of taps of the delay circuit that approximates a predetermined time span. The method can include dynamically adjusting a delay applied to a signal by a delay circuit according to the new tap setting. The delay circuit generates a delayed signal that is provided to the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.