Method to calibrate start values for write leveling in a memory system
US8117483B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2009 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Oct 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller performs a read test for each of a plurality of memory devices to generate a read delay time of each memory device. There is a prime memory device and a subset of memory devices. For each memory device of the subset, the read delay time for the prime memory device is compared with the read delay time of each memory device of the subset of memory devices to generate a differential delay for each memory device of the subset. For each subset memory device, a write test start time of the prime memory device is combined with a differential delay of each memory device to generate a write test start time for the each memory device. A write test for each memory device uses the write test start time for each subset memory device to generate a write launch time for each subset memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.