Structure for implementing memory array device with built in computation capability
US8117567B2 · kind B2 · utility
33Cited by
27References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 28, 2008 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Jul 22, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design structure embodied in a machine readable medium used in a design process includes computational memory device having an array of memory cells arranged in rows and columns, and a pair of read word lines associated with each row of the array. The array is configured to implement, for a given cycle, either a read operation of data contained in a single selected row, or one of a plurality of different bit wise logical operations on data contained in multiple selected rows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.