Determining timing paths within a circuit block of a programmable integrated circuit
US8117577B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2009 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Apr 25, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a map file including a text description of each element within the block diagram, wherein the text description of each element specifies a bypass indicator for the element. The method also can include generating a plurality of sub-paths from the map file, determining timing paths from the plurality of sub-paths by selectively combining different ones of the plurality of sub-paths according to commonality of starting points and ending points of the plurality of sub-paths, and outputting the timing paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.