Architecture cloning for power PC processors
US8117604B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2006 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Jul 14, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/447
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for implementing architecture cloning including: constructing a program call graph in a link phase of interprocedural analysis to model calling relationships between one or more procedures in a program; analyzing the program call graph to obtain information about the program; analyzing the program to identify the one or more procedures subject to architecture cloning; determining feasibility of architecture cloning; marking the one or more procedures in the program suitable for architecture cloning; naming the one or more procedures in the program suitable for architecture cloning; inserting a runtime routine call at an entry point of the program; invoking architecture cloning when one or more candidate procedures are identified during procedure cloning; providing a user with an interface for specifying multiple architecture targets to the compiler; and enabling the compiler to generate architectural specific instructions optimized for each of the multiple architecture targets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.