Manufacturing fan-out wafer level packaging
US8119454B2 · kind B2 · utility
9Cited by
0References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 8, 2008 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Jun 13, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface and a bond pad defined on the top surface, and a substrate having a cavity. An adhesive layer is positioned between a top surface of the cavity and the bottom surface of the integrated circuit, and a bump is positioned proximate a top surface of the fan-out wafer level packaging, the bump spaced apart from the integrated circuit. A redistribution layer is configured to electrically couple the bond pad of the integrated circuit to the bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.