Methods of manufacturing semiconductor devices having a recessed-channel
US8119486B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2011 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Jan 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0275
Abstract
A method according to example embodiments includes forming isolation regions in a substrate, the isolation regions defining active regions. Desired regions of the active regions and the isolation regions are removed, thereby forming recess channel trenches to a desired depth. The recess channel trenches are fog to have a first region in contact with the active regions and a second region in contact with the isolation regions. A width of a bottom surface of the recess channel trenches is less than that of a top surface thereof. The active regions and the isolation regions are annealed to uplift the bottom surface of the recess channel trenches. An area of the bottom surface of the first region is increased. A depth of the bottom surface of the first region is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.