Non-volatile memory device with improved immunity to erase saturation and method for manufacturing same
US8119511B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2011 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Apr 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
Abstract
A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.