Non-volatile memory cell and array

US8120088B1 · kind B1 · utility

Assignee

• Marvell International Ltd. · BM

Inventors

• Min She · Fremont, US
• Chih-Hsin Wang · San Jose, US

Key dates

• Filing date: Apr 18, 2008
• Grant date: Feb 21, 2012
• Expiry date: Dec 22, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/696

Abstract

Memory cells and arrays have reduced bit line resistance. An element conductor is disposed on the top of the bit line to reduce the resistance of the bit line while maintaining a shallow bit line junction so that 200 Ohm/square or lower sheet resistances are achieved with the bit line junctions typically 20 nanometers or shallower while the doping levels in the junctions are below about 5×1019 atoms/cm3.