Flip-flop circuit with internal level shifter
US8120404B2 · kind B2 · utility
2Cited by
9References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2011 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Jul 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356147
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.