Patent · US Active

Multi-die memory, apparatus and multi-die memory stack

US8120958B2 · kind B2 · utility

15Cited by
1References
13Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 24, 2007
Grant dateFeb 21, 2012
Priority date
Expiry dateJun 4, 2028

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C2213/71
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

The multi-die memory comprises a first die and a second die. The first die comprises a first group of memory banks, and the second die comprises a second group of memory banks. The first group of memory banks and the second group of memory banks are coupled to a common memory interface. The common memory interface couples the multi-die memory with an internal connection.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.