Assessing critical dimension and overlay tolerance
US8121396B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 15, 2007 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Dec 21, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/705
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for constructing an error map for a lithography process, by constructing a first error map using spatial error data compiled on a lithography tool used in the lithography process, and constructing a second error map using spatial error data compiled on a mask used in the lithograph process, and then combining the first error map and the second error map to produce an overall error map for the lithography process. In this manner, the spatial error is determined prior to committing product to the process, and excessive error can be corrected or otherwise resolved prior to such commitment. In various embodiments, the spatial error data includes lens error data and stage movement error data. In some embodiments the spatial error data compiled on the mask is constructed by comparing mask pattern placement data to mask pattern source files. Some embodiments include the step of adjusting process variables to reduce errors represented in the overall error map.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.