Tony DiBiase
8Patents
4h-index
4Co-inventors
42Inventor score
Filing activity: Jul 18, 2002 → Aug 27, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7408642B1 | Registration target design for managing both reticle grid error and wafer overlay | Physics | 46 | Active |
| US8104342B2 | Process condition measuring device | Emerging Cross-Sectional Technologies | 8 | Active |
| US6977183B1 | Process for locating, displaying, analyzing, and optionally monitoring potential transient defect sites in one or more integrated circuit chips of a semiconductor substrate | Electricity | 7 | Expired |
| US7846266B1 | Environment friendly methods and systems for template cleaning and reclaiming in imprint lithography technology | Chemistry; Metallurgy | 6 | Active |
| US7924408B2 | Temperature effects on overlay accuracy | Physics | 3 | Active |
| US7987057B1 | Intelligent stitching boundary defect inspection | Physics | 2 | Active |
| US8121396B1 | Assessing critical dimension and overlay tolerance | Physics | 0 | Active |
| US7202094B2 | Process for locating, displaying, analyzing, and optionally monitoring potential transient defect sites in one or more integrated circuit chips of a semiconductor substrate | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.