Systems and methods for masking latency of memory reorganization work in a compressed memory system
US8122216B2 · kind B2 · utility
4Cited by
3References
25Claims
0Family size
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Key dates
| Filing date | Sep 6, 2006 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Oct 22, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.