Method of performing static timing analysis considering abstracted cell's interconnect parasitics
US8122411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2009 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | May 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An abstraction model supporting multiple hierarchical levels is inputted into a generalized static timing analysis of a hierarchical IC chip design to analyze and optimize the design of circuits integral to the chip containing a plurality of macro abstracts. An electrical network, synthesized for an internal abstract interconnect segment, is performed only once per macro and is applied to multiple instances of the macro abstract model in the IC chip design. The synthesized electrical network is a resistive capacitive or a resistive inductive capacitive network or a combination thereof. The synthesized electrical network is then used to match impulse response transfer functions of the network and the abstract interconnect segment's timing model. This network is stitched with the electrical parasitics of external interconnect segments connected to macro primary outputs. Various model order reductions are then performed on the electrical parasitics of external interconnects prior to network stitching. A static timing analysis is performed on the final network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.