Debjit Sinha
36Patents
6h-index
46Co-inventors
65Inventor score
Filing activity: Sep 14, 2007 → Mar 18, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8122404B2 | Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits | Physics | 14 | Active |
| US9342639B1 | Method of hierarchical timing closure of VLSI circuits using partially disruptive feedback assertions | Physics | 11 | Active |
| US7685549B2 | Method of constrained aggressor set selection for crosstalk induced noise | Physics | 9 | Active |
| US7788617B2 | Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis | Physics | 9 | Active |
| US8683409B2 | Performing statistical timing analysis with non-separable statistical and deterministic variations | Physics | 8 | Active |
| US8418107B2 | Performing statistical timing analysis with non-separable statistical and deterministic variations | Physics | 7 | Active |
| US8560989B2 | Statistical clock cycle computation | Physics | 6 | Active |
| US9400864B2 | System and method for maintaining slack continuity in incremental statistical timing analysis | Physics | 6 | Active |
| US8141025B2 | Method of performing timing analysis on integrated circuit chips with consideration of process variations | Physics | 6 | Active |
| US8458632B2 | Efficient slack projection for truncated distributions | Physics | 4 | Active |
| US8103997B2 | Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits | Physics | 4 | Active |
| US8732642B2 | Method for achieving an efficient statistical optimization of integrated circuits | Physics | 3 | Active |
| US10346569B2 | Multi-sided variations for creating integrated circuits | Physics | 3 | Active |
| US8122411B2 | Method of performing static timing analysis considering abstracted cell's interconnect parasitics | Physics | 3 | Active |
| US9690899B2 | Prioritized path tracing in statistical timing analysis of integrated circuits | Physics | 3 | Active |
| US10387682B2 | Parallel access to running electronic design automation (EDA) application | Physics | 2 | Active |
| US8930864B2 | Method of sharing and re-using timing models in a chip across multiple voltage domains | Physics | 1 | Active |
| US9607124B2 | Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints | Physics | 1 | Active |
| US9940431B2 | Accurate statistical timing for boundary gates of hierarchical timing models | Physics | 1 | Active |
| US9836572B2 | Incremental common path pessimism analysis | Physics | 1 | Active |
| US10970455B1 | Apportionment aware hierarchical timing optimization | Physics | 1 | Active |
| US9798843B2 | Statistical timing using macro-model considering statistical timing value entry | Physics | 1 | Active |
| US10831954B1 | Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs | Physics | 1 | Active |
| US10380289B2 | Multi-sided variations for creating integrated circuits | Physics | 0 | Active |
| US10929567B2 | Parallel access to running electronic design automation (EDA) application | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.