Multiple exposure and single etch integration method
US8124534B2 · kind B2 · utility
1Cited by
1References
24Claims
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Key dates
| Filing date | Jul 22, 2008 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Dec 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process including forming a silicon layer over a semiconductor wafer having features thereon and then selectively ion implanting in the silicon layer to form ion implanted regions. The step of selectively ion implanting is repeated as many times as necessary to obtain a predetermined number and density of features. Thereafter, the silicon layer is etched to form openings in the silicon layer that were formerly occupied by the ion implanted regions. The opened areas in the silicon layer form a mask for further processing of the semiconductor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.