Inventor · Albany, NY, US

Jin Z. Wallner

12Patents

4h-index

28Co-inventors

56Inventor score

Filing activity: Jul 22, 2008 → Apr 11, 2019

Most-cited inventions

Patent	Title	Area	Cited by	Status
US9917103B1	Diffusion break forming after source/drain forming and related IC structure	Electricity	15	Active
US9171935B2	FinFET formation with late fin reveal	Electricity	9	Active
US9887135B1	Methods for providing variable feature widths in a self-aligned spacer-mask patterning process	Electricity	6	Active
US8940634B2	Overlapping contacts for semiconductor device	Electricity	4	Active
US7883953B2	Method for transistor fabrication with optimized performance	Electricity	4	Active
US9412843B2	Method for embedded diamond-shaped stress element	Electricity	3	Active
US8787074B2	Static random access memory test structure	Electricity	2	Active
US9899257B1	Etch stop liner for contact punch through mitigation in SOI substrate	Electricity	2	Active
US8124534B2	Multiple exposure and single etch integration method	Electricity	1	Active
US9418982B2	Multi-layered integrated circuit with selective temperature coefficient of resistance	Electricity	1	Active
US10580684B2	Self-aligned single diffusion break for fully depleted silicon-on-insulator and method for producing the same	Electricity	0	Active
US11056591B2	Epitaxial structures of semiconductor devices that are independent of local pattern density	Electricity	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.