Device layout for gate last process
US8125051B2 · kind B2 · utility
15Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 2009 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Apr 1, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
Abstract
A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.