Complementary spin transistor logic circuit
US8125247B2 · kind B2 · utility
6Cited by
6References
19Claims
0Family size
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Key dates
| Filing date | Oct 7, 2010 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Oct 7, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is provided a complementary spin transistor logic circuit, including: a parallel spin transistor that includes a magnetized first source, a first drain magnetized in parallel with the magnetization direction of the first source, a first channel layer and a first gate electrode; and an anti-parallel spin transistor that includes a magnetized second source, a second drain magnetized in anti-parallel with the magnetization direction of the second source, a second channel layer and a second gate electrode, wherein the first gate electrode and the second gate electrode are connected to a common input terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.