Wake-and-go mechanism with system address bus transaction master
US8127080B2 · kind B2 · utility
18Cited by
88References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 1, 2008 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Feb 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/521
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred. In response to the comparison resulting in a determination that the event has not occurred, the wake-and-go engine populates the wake-and-go storage array with the target address and snoops the target address on the system bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.