Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operations
US8127082B2 · kind B2 · utility
2Cited by
2References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2006 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Aug 5, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for allowing multiple devices access to an address translation cache while cache maintenance operations are occurring at the same time. By interleaving the commands requiring address translation with maintenance operations that may normally take many cycles, address translation requests may have faster access to the address translation cache than if maintenance operations were allowed to stall commands requiring address translations until the maintenance operation was completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.