Method and apparatus of ATE IC scan test using FPGA-based system
US8127187B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2009 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Dec 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/25
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus and a method for enhancing the use of automated test equipment (ATE), are presented. The apparatus comprises a test load board that mounts a plurality of devices to be tested (DUTs), and a daughter card communicating with the test board and the ATE, testing each of the plurality of devices, and providing test results to the ATE. The method comprises mounting a plurality of devices to be tested on the test load board, using the daughter card to communicate with the test board and the ATE, and using the daughter card for testing each of the plurality of DUTs, providing test results to the ATE. Also provided is a system to perform automated tests of integrated chips, comprising an ATE scan test unit, an off-load tester resource coupled to the ATE scan test unit, a processor executing commands to control the ATE unit and the off-load tester resource.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.