Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode

US8127192B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Sampan Arora · Bengaluru, IN
• Divya S. Anvekar · Savanuru, IN
• Manoj Dusanapudi · Bengaluru, IN
• Sunil Suresh Hatti · Gokul, IN
• Shakti Kapoor · Austin, US
• Bhavani Shringari Nanjundiah · Bengaluru, IN

Key dates

• Filing date: Jul 14, 2008
• Grant date: Feb 28, 2012
• Expiry date: Oct 14, 2030

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F11/263
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

During a test pattern build, a test pattern generator pseudo-randomly selects an address for a selected lwarx instruction and builds the lwarx instruction using the pseudo-random address into a test pattern. Subsequently, the test pattern generator builds a store instruction after the lwarx instruction using the pseudo-random address. The store instruction is adapted to store the pseudo-random address in a predetermined memory location. The test pattern generator also builds an interrupt service routine that services an interrupt associated with the interrupt request; checks the predetermined memory location; determines that the pseudo-random address is located in the predetermined memory location; and executes a subsequent lwarx instruction using the pseudo-random address.