Semiconductor devices and methods for making the same
US8129778B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2009 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Sep 17, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/343
Abstract
Semiconductor devices and methods for making such devices that are especially suited for high-frequency applications are described. The semiconductor devices combine a SIT (or a junction field-effect transistor [JFET]) architecture with a PN super-junction structure. The SIT architecture can be made using a trench formation containing a gate that is sandwiched between thick dielectric layers. While the gate is vertically sandwiched between the two isolating regions in the trench, it is also connected to a region of one conductivity type of the super-junction structure, thereby allowing control of the current path of the semiconductor device. Such semiconductor devices have a lower specific resistance and capacitance relative to conventional planar gate and recessed gate SIT semiconductor devices. Other embodiments are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.