Techniques for three-dimensional circuit integration

US8129811B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Solomon Assefa · Ossining, US
• Kuan-Neng Chen · Hsinchu, TW
• Steven J. Koester · Toledo, US
• Yuri A. Vlasov · Katonah, US

Key dates

• Filing date: Apr 16, 2011
• Grant date: Mar 6, 2012
• Expiry date: Apr 16, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/00

Abstract

Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.