Method of reducing bit error rate for a flash memory
US8130544B2 · kind B2 · utility
12Cited by
9References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2009 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Nov 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of reducing coupling effect in a flash memory is disclosed. A neighboring page is read, and a flag is set active if the neighboring page is an interfering page. Data are read from the neighboring page at least two more times using at least two distinct read voltages respectively. The threshold-voltage distributions associated with an original page and the neighboring page are transferred according to the read data and the flag.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.