Multi-rank partial width memory modules
US8130560B1 · kind B1 · utility
116Cited by
503References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2007 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Nov 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1678
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is provided for multi-rank, partial-width memory modules. A memory controller is provided. Additionally, a memory bus is provided. Further, a memory module with a plurality of ranks of memory circuits is provided, the memory module including a first number of data pins that is less than a second number of data pins of the memory bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.