Data transfer circuit
US8130570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2010 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Sep 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data transfer circuit includes: an asynchronous memory to which transfer data is written from a first clock domain with a first clock and from which the written transfer data is read to a second clock domain with a second clock; a scan flip-flop whose input terminal is connected to a first position located on a data path, of the transfer data, from the asynchronous memory to the second clock domain, and whose output terminal is connected to a second position located on a data path, of the transfer data, from the asynchronous memory to the first position; and a clock selector which selects a clock to drive the scan flip-flop from the first clock and the second clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.