BIAS voltage generation circuit for an SOI radio frequency switch
US8131225B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2008 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Aug 1, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/213
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A radio frequency (RF) switch located on a semiconductor-on-insulator (SOI) substrate includes at least one electrically biased region in a bottom semiconductor layer. The RF switch receives an RF signal from a power amplifier and transmits the RF signal to an antenna. The electrically biased region may be biased to eliminate or reduce accumulation region, to stabilize a depletion region, and/or to prevent formation of an inversion region in the bottom semiconductor layer, thereby reducing parasitic coupling and harmonic generation due to the RF signal. A voltage divider circuit and a rectifier circuit generate at least one bias voltage of which the magnitude varies with the magnitude of the RF signal. The at least one bias voltage is applied to the at least one electrically biased region to maintain proper biasing of the bottom semiconductor layer to minimize parasitic coupling, signal loss, and harmonic generation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.