Patent · US Active

High speed adder design for a multiply-add based floating point unit

US8131795B2 · kind B2 · utility

2Cited by

5References

11Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Sang Hoo Dhong · San Jose, US
Silvia M. Mueller · Altdorf, DE
Hwa-Joon Oh · Austin, US

Key dates

Filing date	Nov 25, 2008
Grant date	Mar 6, 2012
Priority date	—
Expiry date	Aug 22, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F7/5443
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.