Semiconductor device
US8132063B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2011 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Jul 26, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.