Closed-loop 1×N VLSI design system
US8132134B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2008 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Oct 22, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments that design integrated circuits using a closed loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a viewer and a 1×N compiler. The viewer may generate displays of behavioral representations of 1×N building blocks, with the behavioral representations comprising RTL definitions. The 1×N compiler may create physical design representations of the 1×N building block and create behavioral representations from the physical design representations, wherein the physical design representations have elements altered by one or more tools of a tool suite.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.