Method of manufacturing semiconductor integrated circuit device
US8133795B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2010 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Nov 30, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the present invention, in the exposure to light of a memory cell array or the like of a semiconductor memory or the like, when a group of unit openings for etching the STI trench regions in which the unit openings for etching the STI trench regions each having a rectangular shape are arranged in rows and columns are transferred by the exposure onto a negative resist film, multiple exposure is appropriately used which includes a first exposure step using a first optical mask having a group of first linear openings extending in a column direction and a second exposure step using a second optical mask having a group of second linear openings extending in a row direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.