Nonvolatile semiconductor memory device

US8134203B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Takashi Izumida · Yokohama, JP
• Nobutoshi Aoki · Yokohama, JP

Key dates

• Filing date: Nov 13, 2009
• Grant date: Mar 13, 2012
• Expiry date: Jan 5, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/00

Abstract

In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.