Computation spreading utilizing dithering for spur reduction in a digital phase lock loop
US8134411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2008 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Dec 31, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L1/022
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A novel and useful apparatus for and method of spur reduction using computation spreading with dithering in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over a PLL reference clock period wherein each computation is performed at a much higher processor clock frequency than the PLL reference clock rate. This significantly reduces the per cycle current transient generated by the computations. The frequency content of the current transients is at the higher processor clock frequency which results in a significant reduction in spurs within sensitive portions of the output spectrum. Further reduction in spurs is achieved by dithering the duration of the software loop of atomic operations and/or by randomly shuffling one or more non-data dependent instructions within each iteration of the software loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.