Method and apparatus to reduce footprint of ESD protection within an integrated circuit

US8134813B2 · kind B2 · utility

Assignee

• XILINX, INC. · US

Inventors

• James Karp · Saratoga, US
• Richard C. Li · Mountain View, US
• Fu-Hing Ho · San Francisco, US
• Mohammed Fakhruddin · San Jose, US

Key dates

• Filing date: Jan 29, 2009
• Grant date: Mar 13, 2012
• Expiry date: Jun 7, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/811

Abstract

An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground.