Dynamic leakage control for memory arrays
US8134874B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2009 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | May 1, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit is disclosed that comprises a plurality of memory cells coupled to a virtual voltage rail. The plurality of memory cells may form, for example, a sub-array of an SRAM array. A switching circuit may be coupled between the virtual voltage rail and a voltage supply node, and a comparator may be coupled to compare a voltage level present on the virtual voltage rail to a reference voltage to thereby provide an output signal based on the comparison. The switching circuit may be configured to electrically couple the virtual voltage rail to the voltage supply node depending upon the output signal. In some embodiments, the switching circuit may be implemented using either a PMOS transistor or an NMOS transistor, although other embodiments may employ other switching circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.