Signal calibration for memory interface
US8134878B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2010 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Oct 1, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1774
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of calibrating memory controller signals within an integrated circuit (IC) can include determining an internal delay of a clock network of the IC and generating a calibrated clock signal by applying a first delay to an uncalibrated clock signal, wherein the first delay is determined by subtracting the internal delay of the clock network of the IC from a bitperiod of the uncalibrated clock signal. The method can include determining a classification of at least one data signal according to timing of positive and negative edges of the at least one data signal in comparison with edges of the calibrated clock signal and aligning at least one of positive or negative edges of the at least one data signal to occur at midpoints between edges of the calibrated clock signal according to the classification of the at least one data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.