Validating manufacturing test rules pertaining to an electronic component
US8135571B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2008 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Dec 19, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention is directed to validating a specified manufacturing test rule, which pertains to an electronic component. The method includes generating a file of test data sets, wherein each test data set in the file is valid for the rule. Each test data set includes a stimulus comprising one or more single input vectors, and further includes a set of results that are expected. The method further comprises constructing a testbench to prepare testcases for simulation, wherein each testcase corresponds to the stimulus and the expected output results of one of the test data sets, and each testcase is disposed to be simulated separately, or independently, from every other testcase. The method further comprises selectively preparing each of the testcases for simulation, in order to provide simulated results for the stimulus corresponding to each testcase. The expected results and the simulated results are compared for each testcase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.