Leveraging low-latency memory access
US8135723B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2008 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Mar 30, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/90335
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computational units of any task may run in different silos. In an embodiment, a search query may be evaluated efficiently on a non-uniform memory architecture (NUMA) machine, by assigning separate chunks of the index to separate memories. In a NUMA machine, each socket has an attached memory. The latency time is low or high, depending on whether a processor accesses data in its attached memory or a different memory. Copies of an index manager program, which compares a query to an index, run separately on different processors in a NUMA machine. Each instance of the index manager compares the query to the index chunk in the memory attached to the processor on which that instance is running. Thus, each instance of the index manager may compare a query to a particular portion of the index using low-latency accesses, thereby increasing the efficiency of the search.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.